Trigger control register
| TR_SEL | Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of ‘0’, and as a result will not cause HW activation of the output trigger. |
| TR_INV | Specifies if the output trigger is inverted. |
| TR_EDGE | Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive sensitive trigger. ‘0’: level sensitive. ‘1’: edge sensitive trigger. The (inverted) ouput trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) ouput trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. |